Conventionally, depletion type MOS transistors have been used to form reference voltage circuits with high output voltage accuracy. The depletion type MOS transistor is a device that is formed by implanting impurity ions into an enhancement type MOS transistor so that current can flow even when a gate-source voltage is zero. A masked ROM is a device that is formed by changing part of MOS transistors arranged in the form of a matrix into resistance. Conventionally, in a power management-associated apparatus, such as a portable equipment, a digital circuit having a masked ROM and a reference voltage generating circuit supplying power to the digital circuit are installed in different IC chips.
In such a power management-associated apparatus, such as a portable equipment, however, it is desirable to provide such a digital circuit comprised of a depletion type MOS transistor in a single IC chip. It is also desirable to minimize the steps of manufacturing the depletion type MOS transistor to reduce number of parts and cost, while simplifying the manufacturing process.
Accordingly, there is a need for a semiconductor integrated circuit device that integrates the depletion MIS transistor, the transistor forming a masked ROM, and a submicron CMOS on a single semiconductor substrate, while minimizing the steps of manufacturing the same. The present invention addresses this need.